/*
 * lcd.h
 *
 *  Created on: 2009-07-30
 *      Author: USER
 */

#ifndef LCD_H_CORTEX
#define LCD_H_CORTEX
//#include "LPC23xx.h"
//#include "LPC2478.h"
#include "LPC177x_8x.h"


//=============jaki wyswietlacz
#define PCBNOTYPE 0x00
#define PCBNEC 0x01
#define PCBTOSHI 0x02
#define PCBGET07 0x03
#define PCBGET07_INVCLK 0x04
#define PCBGET035 0x05


//============================


#define _SBF(f,v) (((unsigned int)(v)) << (f))
#define _BIT(n)	(((unsigned int)(1)) << (n))
#define _BITMASK(field_width) ( _BIT(field_width) - 1)


#define LAMP_SET  LPC_GPIO1->PIN |= (1<<3)
//FIO1SET = (1<<3)
#define LAMP_CLR  LPC_GPIO1->PIN &= ~(1<<3);
//FIO1CLR = (1<<3)

#define LCD_POWER_CLR  LPC_GPIO2->PIN |= (1<<0)
//FIO2SET = (1<<0)
#define LCD_POWER_SET  LPC_GPIO2->PIN &= ~(1<<0)
//FIO2CLR = (1<<0);


#define P027_CLR  LPC_GPIO0->PIN |= (1<<27)
//FIO0SET = (1<<27)
#define P027_SET  LPC_GPIO0->PIN &= ~(1<<27)
//FIO0CLR = (1<<27)

#define NOR_SET  LPC_GPIO0->PIN |= (1<<24)
//FIO0SET = (1<<24)
#define NOR_CLR  LPC_GPIO0->PIN &= ~(1<<24)
//FIO0CLR = (1<<24)

#define PWM_LAMP_SET  LPC_GPIO1->PIN &= ~(1<<7)
//FIO1CLR = (1<<7)
#define PWM_LAMP_CLR  LPC_GPIO1->PIN |= (1<<7)
//FIO1SET = (1<<7)



/* LCD palette register type */
typedef struct
{
  unsigned int Rl:5;
  unsigned int Gl:5;
  unsigned int Bl:5;
  unsigned int Il:1;
  unsigned int Ru:5;
  unsigned int Gu:5;
  unsigned int Bu:5;
  unsigned int Iu:1;
} PALETTE_ENTRY_T;

/* LCD device commands (IOCTL commands) */
typedef enum {
  LCD_SET_BUFFER,        /* Set LCD display frame buffer,
                            arg = memory pointer for image to be displayed */
  LCD_CRSR_SET_BUFFER,   /* Set LCD display frame buffer,
                            arg = memory pointer for image to be displayed */
  LCD_PWR_ON,            /* Turn on the LCD controller power, arg = 1, turn on,
                            arg = 0, turn off */
  LCD_ENABLE,            /* Enable the LCD controller, arg = 1, enable,
                            arg = 0, disable */
  LCD_CRSR_ENABLE,       /* Enable the LCD cursor, arg = 1, enable,
                            arg = 0, disable */
  LCD_CRSR_NUM,          /* Select the LCD cursor number, arg = 0, 64x64,
                            arg = 0, 1, 2, 3, 32x32 */
  LCD_CRSR_SIZE,         /* Set the LCD cursor size, arg = 1, 64x64,
                            arg = 0, 32x32 */
  LCD_CRSR_SYNC,         /* Set the LCD cursor frame sync, arg = 1, sync,
                            arg = 0, async */
  LCD_LOAD_PALETTE,      /* This function supports loading of the color
                            palette from the C file generated by the bmp2c utility.
                            It expects the palette to be passed as an array of 32-bit
                            BGR entries having the following format:
                            7:3 - Blue
                            2:0 - Not used
                            15:11 - Green
                            10:8 - Not used
                            23:19 - Red
                            18:16 - Not used
                            31:24 - Not used
                            arg = pointer to input palette table address*/
  LCD_CRSR_LOAD_PALETTE0, /* 7:0 - Red
                             15:8 - Green
                             23:16 - Blue
                             31:24 - Not used*/
  LCD_CRSR_LOAD_PALETTE1, /* 7:0 - Red
                             15:8 - Green
                             23:16 - Blue
                             31:24 - Not used*/
  LCD_SET_BPP,            /* Set current display bits per pixel,
                             arg = bits per pixel */
  LCD_SET_BGR,            /* LCD invert the bgr bit in the LCD controller.
                             arg = 1, invert BGR for reverse color, arg = 0, BGR for normal color */
  LCD_SET_INTERRUPT,      /* Set interrupt mask set/clear register */
  LCD_CLR_INTERRUPT,      /* Set interrupt clear register*/
  LCD_CRSR_SET_INTERRUPT, /* Set cursor interrupt mask set/clear register */
  LCD_CRSR_CLR_INTERRUPT, /* Set cursor interrupt clear register*/
  LCD_CRSR_XY,            /* Set LCD cursor xy position register */
  LCD_CRSR_CLIP,          /* Set LCD cursor clip position register */
  LCD_GET_STATUS,          // Get a lcd status, use an argument type of LCD_IOCTL_STS_T as the argument to return the correct status
  LCD_DMA_ON_4MT
} LCD_IOCTL_CMD_T;

/* LCD bits per pixel types */
typedef enum {
  BPP_IS_1 = 1,
  BPP_IS_2,
  BPP_IS_4,
  BPP_IS_8,
  BPP_IS_16,
  BPP_IS_24,
  BPP_IS_16_565_MODE,
  BPP_IS_12_444_MODE
} LCD_BPP_T;

/* LCD device arguments for LCD_GET_STATUS command (IOCTL arguments) */
typedef enum {
  LCD_GET_BUFFER,         /* Returns LCD fram buffer address */
  LCD_GET_BPP,            /* Returns current LCD panel bit per pixel */
  LCD_GET_PALETTE,        /* Returns a pointer to palette table */
  LCD_CRSR_GET_PALETTE0,  /* Returns a pointer to cursor palette table */
  LCD_CRSR_GET_PALETTE1,  /* Returns a pointer to cursor palette table */
  LCD_GET_INTERRUPT,      /* Get interrupt mask sstatus register */
  LCD_CRSR_GET_INTERRUPT  /* Get cursor interrupt mask sstatus register */
} LCD_IOCTL_STS_T;

/***********************************************************************
 * Color LCD controller horizontal axis plane control register definitions
 **********************************************************************/
/* Color LCD controller Register Structure */
typedef struct
{
  volatile unsigned int lcdtiming0;         /* LCD horizontal axis plane control register */
  volatile unsigned int lcdtiming1;         /* LCD vertical axis plane control register */
  volatile unsigned int lcdtiming2;         /* LCD clock and signal polarity control register */
  volatile unsigned int lcdtiming3;         /* LCD line end control register */
  volatile unsigned int lcdupbase;          /* LCD upper plane frame base address register */
  volatile unsigned int lcdlpbase;          /* LCD lower plane frame base address register */
  volatile unsigned int lcdctrl;            /* LCD control register */
  volatile unsigned int lcdimsc;            /* LCD interrupt mask set/clear register */
  volatile unsigned int lcdris;             /* LCD raw interrupt status register */
  volatile unsigned int lcdmis;             /* LCD masked interrupt status register */
  volatile unsigned int lcdicr;             /* LCD interrupt clear register */
  volatile unsigned int lcdupcurr;          /* LCD upper panel current address value register */
  volatile unsigned int lcdlpcurr;          /* LCD lower panel current address value register */
  volatile unsigned int reservedclcdc0[115];/* LCD reserved */
  volatile unsigned int lcdpalette[128];    /* LCD palette registers */
  volatile unsigned int reservedclcdc1[256];/* LCD reserved */
  volatile unsigned int cursorimage[256];   /* LCD cursor image */
  volatile unsigned int clcdcrsrctrl;       /* LCD cursor control register */
  volatile unsigned int clcdcrsrconfig;     /* LCD cursor configuration register */
  volatile unsigned int clcdcrsrpalette0;   /* LCD cursor palette register */
  volatile unsigned int clcdcrsrpalette1;   /* LCD cursor palette register */
  volatile unsigned int clcdcrsrxy;         /* LCD cursor xy position register */
  volatile unsigned int clcdcrsrclip;       /* LCD cursor clip position register */
  volatile unsigned int reservedclcdc2[2];  /* LCD reserved */
  volatile unsigned int lcdcrsrimsc;        /* LCD cursor interrupt mask set/clear register */
  volatile unsigned int lcdcrsrris;         /* LCD cursor raw interrupt status register */
  volatile unsigned int lcdcrsrmis;         /* LCD cursor masked interrupt status register */
  volatile unsigned int lcdcrsricr;         /* LCD cursor interrupt clear register */
} CLCDC_REGS_T;


/* LCD controller horizontal axis plane control register pixels per line */
#define CLCDC_LCDTIMING0_PPL_WIDTH 6
#define CLCDC_LCDTIMING0_PPL(n) _SBF(2, (((n) / 16) - 1) & _BITMASK(CLCDC_LCDTIMING0_PPL_WIDTH))
/* LCD controller horizontal axis plane control register HSYNC pulse width */
#define CLCDC_LCDTIMING0_HSW_WIDTH 8
#define CLCDC_LCDTIMING0_HSW(n) _SBF(8, ((n) - 1) & _BITMASK(CLCDC_LCDTIMING0_HSW_WIDTH))
/* LCD controller horizontal axis plane control register horizontal front porch */
#define CLCDC_LCDTIMING0_HFP_WIDTH 8
#define CLCDC_LCDTIMING0_HFP(n)	_SBF(16, ((n) - 1) & _BITMASK(CLCDC_LCDTIMING0_HFP_WIDTH))
/* LCD controller horizontal axis plane control register horizontal back porch */
#define CLCDC_LCDTIMING0_HBP_WIDTH 8
#define CLCDC_LCDTIMING0_HBP(n)	_SBF(24, ((n) - 1) & _BITMASK(CLCDC_LCDTIMING0_HBP_WIDTH))

/***********************************************************************
 * Color LCD controller vertical axis plane control register definitions
 **********************************************************************/

/* LCD controller vertical axis plane control register lines per panel */
#define CLCDC_LCDTIMING1_LPP_WIDTH 10
#define CLCDC_LCDTIMING1_LPP(n)	_SBF(0, ((n) - 1) & _BITMASK(CLCDC_LCDTIMING1_LPP_WIDTH))
/* LCD controller vertical axis plane control register VSYNC pulse width */
#define CLCDC_LCDTIMING1_VSW_WIDTH 6
#define CLCDC_LCDTIMING1_VSW(n)	_SBF(10, ((n) - 1) & _BITMASK(CLCDC_LCDTIMING1_VSW_WIDTH))
/* LCD controller vertical axis plane control register vertical front porch */
#define CLCDC_LCDTIMING1_VFP_WIDTH 8
#define CLCDC_LCDTIMING1_VFP(n)	_SBF(16, (n) & _BITMASK(CLCDC_LCDTIMING1_VFP_WIDTH))
/* LCD controller vertical axis plane control register vertical back porch */
#define CLCDC_LCDTIMING1_VBP_WIDTH 8
#define CLCDC_LCDTIMING1_VBP(n)	_SBF(24, (n) & _BITMASK(CLCDC_LCDTIMING1_VBP_WIDTH))

/***********************************************************************
 * Color LCD controller clock and signal polarity control register definitions
 **********************************************************************/

/* LCD controller clock and signal polarity control register panel clock divisor low*/
#define CLCDC_LCDTIMING2_PCD_LO_WIDTH 5
#define CLCDC_LCDTIMING2_PCD_LO(n) _SBF(0, ((n) - 2) & _BITMASK(CLCDC_LCDTIMING2_PCD_LO_WIDTH))
/* LCD controller clock and signal polarity control register clock select */
#define CLCDC_LCDTIMING2_CLKSEL _BIT(5)
/* LCD controller clock and signal polarity control register AC bias pin frequency */
#define CLCDC_LCDTIMING2_ACB_WIDTH 5
#define CLCDC_LCDTIMING2_ACB(n)	_SBF(6, ((n) - 1) & _BITMASK(CLCDC_LCDTIMING2_ACB_WIDTH))
/* LCD controller clock and signal polarity control register invert VSYNC */
#define CLCDC_LCDTIMING2_IVS    _BIT(11)
/* LCD controller clock and signal polarity control register invert HSYNC */
#define CLCDC_LCDTIMING2_IHS    _BIT(12)
/* LCD controller clock and signal polarity control register invert plane clock */
#define CLCDC_LCDTIMING2_IPC    _BIT(13)
/* LCD controller clock and signal polarity control register invert output enable */
#define CLCDC_LCDTIMING2_IOE    _BIT(14)
/* LCD controller clock and signal polarity control register clocks per line */
#define CLCDC_LCDTIMING2_CPL_WIDTH 10
#define CLCDC_LCDTIMING2_CPL(n)	_SBF(16, (n) & _BITMASK(CLCDC_LCDTIMING2_CPL_WIDTH))
/* LCD controller clock and signal polarity control register bypass pixel clock divider */
#define CLCDC_LCDTIMING2_BCD 	_BIT(26)
/* LCD controller clock and signal polarity control register panel clock divisor high*/
#define CLCDC_LCDTIMING2_PCD_HI_WIDTH 5
#define CLCDC_LCDTIMING2_PCD_HI(n) _SBF((27 - CLCDC_LCDTIMING2_PCD_LO_WIDTH), ((n) - 2) & _SBF(CLCDC_LCDTIMING2_PCD_LO_WIDTH, _BITMASK(CLCDC_LCDTIMING2_PCD_HI_WIDTH)))

/**********************************************************************
 * Color LCD Controller line end control register definitions
 *********************************************************************/

/* Line End Signal Delay */
#define CLCDC_LCDTIMING3_LED_WIDTH 7
#define CLCDC_LCDTIMING3_LED(n) _SBF(0, ((n) - 1) & _BITMASK(CLCDC_LCDTIMING3_LED_WIDTH))
/* Line End Enable */
#define CLCDC_LCDTIMING3_LEE    _BIT(16)

/***********************************************************************
 * Color LCD controller interrupt mask set/clear register definitions
 * Color LCD controller raw interrupt status register definitions
 * Color LCD controller masked interrupt status register definitions
 * Color LCD controller interrupt clear register definitions
 **********************************************************************/

/* FIFO underflow bit */
#define CLCDC_LCD_INTERRUPT_FUF     _BIT(1)
/* LCD next base address update bit */
#define CLCDC_LCD_INTERRUPT_LNBU 	_BIT(2)
/* vertical compare bit */
#define CLCDC_LCD_INTERRUPT_VCOMP 	_BIT(3)
/* AHB master error interrupt bit */
#define CLCDC_LCD_INTERRUPT_MBERROR	_BIT(4)

/***********************************************************************
 * Color LCD controller control register definitions
 **********************************************************************/

/* LCD control enable bit */
#define CLCDC_LCDCTRL_ENABLE    _BIT(0)
/* LCD control 1 bit per pixel bit field */
#define CLCDC_LCDCTRL_BPP1      _SBF(1, 0)
/* LCD control 2 bits per pixel bit field */
#define CLCDC_LCDCTRL_BPP2      _SBF(1, 1)
/* LCD control 4 bits per pixel bit field */
#define CLCDC_LCDCTRL_BPP4      _SBF(1, 2)
/* LCD control 8 bits per pixel bit field */
#define CLCDC_LCDCTRL_BPP8      _SBF(1, 3)
/* LCD control 16 bits per pixel bit field */
#define CLCDC_LCDCTRL_BPP16     _SBF(1, 4)
/* LCD control 24 bits per pixel bit field */
#define CLCDC_LCDCTRL_BPP24     _SBF(1, 5)
/* LCD control 16 bits (5:6:5 mode) per pixel bit field */
#define CLCDC_LCDCTRL_BPP16_565_MODE _SBF(1, 6)
/* LCD control 12 bits (4:4:4 mode) per pixel bit field */
#define CLCDC_LCDCTRL_BPP12_444_MODE _SBF(1, 7)
/* LCD control mono select bit */
#define CLCDC_LCDCTRL_BW_COLOR  _SBF(4, 0)
#define CLCDC_LCDCTRL_BW_MONO   _SBF(4, 1)
/* LCD controler TFT select bit */
#define CLCDC_LCDCTRL_TFT       _BIT(5)
/* LCD control monochrome LCD has 4-bit/8-bit select bit */
#define CLCDC_LCDCTRL_MON8      _BIT(6)
/* LCD control dual panel select bit */
#define CLCDC_LCDCTRL_DUAL      _BIT(7)
/* LCD control RGB or BGR format select bit */
#define CLCDC_LCDCTRL_RGB       _SBF(8, 0)
#define CLCDC_LCDCTRL_BGR       _SBF(8, 1)
/* LCD control big-endian byte order select bit */
#define CLCDC_LCDCTRL_BEBO      _BIT(9)
/* LCD control big-endian pixel order within a byte select bit */
#define CLCDC_LCDCTRL_BEPO      _BIT(10)
/* LCD control power enable bit */
#define CLCDC_LCDCTRL_PWR       _BIT(11)
/* LCD control VCOMP interrupt is start of VSYNC */
#define CLCDC_LCDCTRL_VCOMP_VS  _SBF(12, 0)
/* LCD control VCOMP interrupt is start of back porch */
#define CLCDC_LCDCTRL_VCOMP_BP  _SBF(12, 1)
/* LCD control VCOMP interrupt is start of active video */
#define CLCDC_LCDCTRL_VCOMP_AV  _SBF(12, 2)
/* LCD control VCOMP interrupt is start of front porch */
#define CLCDC_LCDCTRL_VCOMP_FP  _SBF(12, 3)
/* LCD control watermark level is 8 or more words free bit */
#define CLCDC_LCDCTRL_WATERMARK _BIT(16)

/* Point to the Color LCD Controller registers */
#define CLCDC ((CLCDC_REGS_T *)(LCD_BASE))



//******************************************************************************
// LCD display types
//******************************************************************************
typedef enum
{
  TFT = 0,      /* Panel type is standard TFT */
  ADTFT,        /* Panel type is advanced TFT */
  HRTFT,        /* Panel type is highly reflective TFT */
  MONO_4BIT,    /* Panel type is 4-bit mono */
  MONO_8BIT,    /* Panel type is 8-bit mono */
  CSTN          /* Panel type is color STN */
} LCD_PANEL_T;


//******************************************************************************
// Structure containing the parameters for the LCD panel
//******************************************************************************
typedef struct
{
  unsigned char           h_back_porch;         /* Horizontal back porch in
                                             clocks (minimum of 1) */
  unsigned char           h_front_porch;        /* Horizontal front porch in
                                             clocks (minimum of 1) */
  unsigned char           h_sync_pulse_width;   /* HSYNC pulse width in
                                             clocks (minimum of 1) */
  unsigned short          pixels_per_line;      /* Pixels per line (horizontal
                                             resolution) */
  unsigned char           v_back_porch;         /* Vertical back porch in
                                             clocks */
  unsigned char           v_front_porch;        /* Vertical front porch in
                                             clocks */
  unsigned char           v_sync_pulse_width;   /* VSYNC pulse width in
                                             clocks (minimum 1 clock) */
  unsigned short          lines_per_panel;      /* Lines per panel (vertical
                                             resolution) */
  unsigned char           invert_output_enable; /* Invert output enable, 1 =
                                             invert*/
  unsigned char           invert_panel_clock;   /* Invert panel clock, 1 =
                                             invert*/
  unsigned char           invert_hsync;         /* Invert HSYNC, 1 = invert */
  unsigned char           invert_vsync;         /* Invert VSYNC, 1 = invert */
  unsigned char           ac_bias_frequency;    /* AC bias frequency in
                                             clocks (minimum 1) */
  unsigned char           bits_per_pixel;       /* Maximum bits per pixel the
                                             display supports */
  unsigned int          optimal_clock;        /* Optimal clock rate (Hz) */
  LCD_PANEL_T     lcd_panel_type;       /* LCD panel type */
  unsigned char           dual_panel;           /* Dual panel, 1 = dual panel
                                             display */

  /* The following parameters are needed for ADTFT and HRTFT panels
     only. For all other panels, these should be programmed to 0 */
  unsigned char           hrtft_cls_enable;     /* HRTFT CLS enable flag, 1 =
                                             enable */
  unsigned char           hrtft_sps_enable;     /* HRTFT SPS enable flag, 1 =
                                             enable */
  unsigned char           hrtft_lp_to_ps_delay; /* HRTFT LP to PS delay in
                                             clocks */
  unsigned char           hrtft_polarity_delay; /* HRTFT polarity delay in
                                             clocks */
  unsigned char           hrtft_lp_delay;       /* HRTFT LP delay in clocks */
  unsigned char           hrtft_spl_delay;      /* HRTFT SPL delay in
                                             clocks */
  /* HRTFT SPL to CLKS delay */
  unsigned short          hrtft_spl_to_cls_delay;
}LCD_PARAM_T ;



typedef struct
{
  unsigned int init;        //Device initialized flag
  CLCDC_REGS_T *regptr; 	// Pointer to LCD registers
  LCD_PARAM_T *dptr;     	//Pointer to LCD controller settings
} CLCDC_CFG_T;

#ifdef __cplusplus
extern "C" {
#endif

void vLCD_Init(void);
void lcd_switch_screen(void);
void lcd_update_screen(void);
long lcd_open(/*void *lcdbase,*/ long arg);
uint8_t lcd_initialize(CLCDC_CFG_T *lcdcfgptr);
long lcd_ioctl(long devid, long cmd, long arg);
void lcd_configure_gpio(void);
//unsigned int Setlcdptr(unsigned int x, unsigned int y);

#ifdef __cplusplus
}
#endif

#endif /* LCD_H_ */
